The invention relates, in general, to flash memory devices and, more particularly, to a method of manufacturing a flash memory device in which interference between floating gates can be reduced and the coupling ratio can be increased.
In a NAND flash memory device, a plurality of cells for storing data are connected in series to form one string. A drain select transistor and a source select transistor are formed between the cell string and the drain and between the cell string and the source, respectively. In the cell of the NAND flash memory device, a gate in which a tunnel oxide layer, a floating gate, a dielectric layer and a control gate are stacked is formed at a specific region on a semiconductor substrate. Junctions are formed at both sides of the gate.
In the NAND flash memory device constructed above, the state of the cell is influenced by the operation of neighboring cells. It is therefore very important to maintain a constant cell state. A phenomenon in which the state of the cell is changed due to the operation of neighboring cells (i.e., a program operation) is called an interference phenomenon. In other words, if a second cell adjacent to a first cell to be read is programmed, a threshold voltage higher than that of the first cell is read due to a capacitance phenomenon caused by a change in the charges of the floating gate of the second cell. Therefore, although the charge of the floating gate of the first cell is not changed, the actual state of the first cell appears distorted due to a change in the state of neighboring cells. The state of the cell is changed due to the interference phenomenon, resulting in a degraded yield of the failure ratio. Accordingly, it is desirable to maintain a constant cell state by minimizing the interference phenomenon.
Meanwhile, in a manufacturing process of a general NAND flash memory device, part of the isolation layer and the floating gate is formed using a Self-Aligned Shallow Trench Isolation (SA-STI) process. The process is described below with reference to FIG. 1.
A tunnel oxide layer 11 and a first polysilicon layer 12 are formed over a semiconductor substrate 10. Specific regions of the first polysilicon layer 12 and the tunnel oxide layer 11 are etched. The semiconductor substrate 10 is etched to a specific depth, forming trenches. The trenches are filled with an insulating layer. A polish process is then performed to form isolation layers 13 in the trenches. Thereafter, a second polysilicon layer 14 is formed and then etched to form floating gates 12 and 14. A dielectric layer 15 and a third polysilicon layer 16 for a control gate are formed over the floating gates 12 and 14.
If the flash memory device is fabricated by the SA-STI process described above, interference may occur between the first polysilicon layers 12 because the isolation layers 13 are formed between neighboring first polysilicon layers 12 serving as the floating gates.
FIG. 2 is a graph illustrating the floating gate interference coupling ratio as a function of floating gate height and the gate-to-gate distance between floating gates of a flash memory device.
Referring to FIG. 2, inter-gate interference is inversely proportional to the distance between the floating gates and proportional to the height of the floating gate. In other words, if the distance between the floating gates increases and the height of the floating gate decreases, interference is reduced. However, if the height of the floating gate decreases, the interface area of the floating gate and the control gate is reduced and the coupling ratio is reduced.